FPGA Implementation of 2D-DWT and SPIHT Architecture for Lossless Medical Image Compression

This paper presents an analysis of wavelet filters and SPIHT encoding techniques adopted in compression and decompression of medical images. The hardware implementation for loss less compression with tradeoff in area, timing and power, requires quantizing of filter coefficients and identification of its impact on reconstruction process. This study proposes a novel algorithm that replaces multipliers with shift operators exploiting the symmetric property of filter coefficients. The filter coefficients are scaled to integers and represented using 9-bit signed representation to ensure that the quantization error is less than 20dB. The HDL code is developed in Verilog for the modified filter architecture in 1D and 2D DWT processor is implemented on Virtex-5 FPGA. The modified algorithm occupies less than 12% slices, operates at frequency of 298 MHz consuming less than 1W of power. The results of the study demonstrate that the hardware design matches with the software model and hence does not result in any loss therefore suitable for loss less medical image compression. Key words— Medical image compression, DWT, Multiplierless logic, quantization effects, lossless compression